Integrated circuits may be provided with ESD protection circuits to protect the integrated circuit (IC) from any electrostatic charge which may be potentially damaging.
The ESD protection is generally applied to the IC's I/O pads or pins. The protection may comprise a high conductance path from the I/O pads to a voltage supply pin. Typically, each and every I/O pin is connected to the positive and negative supply pins by normally reverse bias diodes. However, during an ESD event these diodes may be forward or reversed biased. As is well known, reverse bias diodes provide higher voltage discharge paths for ESD than forward biased diodes. Power dissipated in a reverse bias diode due to an ESD event is a multiple higher than the same diode when forward biased. Therefore, reverse bias diodes used in ESD discharge paths require larger size junction areas than forward biased diodes. Accordingly, it is preferable to avoid using reverse bias diodes in the ESD discharge paths.
In connection with diode ESD paths, a clamping circuit has been used. The clamping circuit is typically connected across the power supply. The clamp provides conduction at a voltage higher than the supply but lower than the breakdown voltage of the back biased I/O protection diodes. The clamp has been used to bypass the back bias I/O protection diodes reducing their size requirement by reducing their power dissipation requirement.
While the addition of a clamp provides a greater level of ESD protection, the clamp voltage must still be set higher than the supply voltage. Therefore, the conduction voltage of all the ESD discharge paths through the supply clamp will be higher than the normal supply voltage.
Accordingly, ESD protection using I/O protection diodes with or without clamping cannot provide low voltage protection, less than a normal supply voltage.